Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. As the Front End Methodology Engineer, you will be responsible for developing and maintaining the Register Transfer Level (RTL) design flows and methodologies for our cutting edge chip productions. Throughout the program you will be interacting with various teams, including architecture, front end design, verification, design for testing( DFT) and physical design to ensure quality, performance and efficiency of RTL code and tools.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

Responsibilities

• Architect and implement workflows using industry-standard tools and best practices that aid in System on a Chip (SOC) assembly including RTL handoff between Intellectual Property (IPs)/subsystems/SOC/DFT teams, hierarchy manipulation and feedthrough methodologies, constraint and waiver promotion, specification to design collateral flows etc.

• Provide guidance and training to the RTL design team on usage of the flows and methodologies

• Collaborate with RTL design, verification, DFT and Physical design teams to resolve any issues related to RTL code, tools or flows

• Evaluate new tools, technologies and standards for RTL design and propose improvements and enhancements

• Document and maintain the RTL design flows and methodologies

Qualifications

Required/Minimum Qualifications

• 9+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

• ORDoctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

• 8+ years of experience delivering successful Front End design using System Verilog or other Hardware Description Languages (HDL) languages

• 8+ years expertise in developing and deploying various Front End tools, flows and methodologies such as Lint, Clock Domain Crossing (CDC),Reset Domain Crossing (RDC), Synthesis

• 4+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP, subsystem and full chip SOC

Other Requirements

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Addtional or Preferred Qualifications

• 15+ years technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.

• 14+ years expertise in developing and deploying various Front End tools, flows and methodologies such as Lint, CDC, RDC and Synthesis

• 14+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP, subsystem and full chip SOC

• Proven track record of architecting and implementing Front End RTL methodologies for multiple SOCs

• Thorough understanding of end-to-end SOC design cycles and dependencies between design, verification, physical design, DFT teams

• Experience working with global design, verification, physical design and product teams

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until May 16, 2024.

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .