Job Description

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your will directly drive and work with DE cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meets customer needs.

This support role will drive the solutions for Reliability Verification (RV) - ESD/HVEOS/Latch-Up issues when customers use intel PDK collaterals in RV tools/flows. You will lead the collaboration and communication across TD/DE/QnR organizations to find the best path to resolve the issue. Tasks also include owning/maintaining training documents, user guide, and customer ticket support.

As a DEAS (Design Enablement Application and Support) key member, you will need to have good communication skills to interact with customers directly, apply analytical problem-solving capability to identify the key requests, root-causing the issue, and do teamwork with DE stakeholders to support and enable customer success.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related field .

6+ years of experience in three or more of the following areas:

• Industry direct experience to support customers in ESD/HVEOS/LU reliability related fields, in terms of technology, or EDA tools.

• Experienced in ESD checking tools like PERC or Pathfinder, with strong skill set and knowledge to debug root cause of failures.

-Familiarity with semiconductor reliability physics and failure mechanisms like latch-up (LU), and electrostatic discharge (ESD), Electrical Over Stress (EOS).

• Intel and/or external foundry process technology knowledge in advance nodes

Preferred Qualifications:

6+ years of experience in Intel and/or external foundry process technology knowledge in advance nodes.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.