Job Description

ISCP (IP, Security and Client Product) team focus on IP development and SOC (system on chip) architecture definition, design, verification, security execution to deliver high quality products to market. We deliver SOCs that feed the mainstream markets of various platforms in desktop, mobile, and automotive. We are looking to hire a Product Security Micro Architect engineer with technical experience in SOC/IP design to be part of the reviews and assessment of the SOC and IPs security architecture to drive SOC micro architecture security assurance in compliance to Intel Security Development Lifecycle (SDL).

Responsible for the review of the SOC, IPs architecture, micro architecture, design, flows supporting SOC security objectives with regard to platform objectives, threat modeling and security risk analysis. Requires understanding of multiple system areas in an SOC architecture and micro architecture. This role works in cross-site collaboration with SOC product(s) architecture teams, micro architects and other business units like IPAS (Intel Product Assurance and Security), other SOC pre-Silicon security teams within Intel to leverage best known methods (BKM), tools, flows to meet SOC product security assurance before our SOC products tape-in.

In this role responsibilities may include although not limited to

• Drives SDL (security development lifecycle) S2 stage by conducting micro RTL (design) code reviews of IP feature to ensure no security vulnerability.

• Works with SOC security and validation architect to review and defined correct IPs security parameters.

• Participate in SOC's features/functions architecture SAFE (Security Architecture Forum) security reviews, threat model reviews working closely with the SOC security and functional architecture to ensure feature definition and micro architecture conform to security assurance standards per Intel.

• Conducts Design Hackathons with SOC micro-architect/security architect partners with the objective to identify any security vulnerabilities in complex areas of the SOC flows so that the design is corrected prior to the SOC product tape-in.

• Works effectively and get results in a cross functional team environment throughout product life cycle.

• Ability to collaborate with cross functional IP hardware design teams, SOC security architects, micro architects and firmware teams to solve complex issues to meet security assurance of the SOC.

• Drives PSIRTs (product security issue response team) assessment and analysis of potential security vulnerabilities that may affect Intel products to come up with solution(s) for all impacted SOC products.

• Review test scenarios spanning multiple SoC domains.

• Continuous engagement and adoption of IPAS and ISCP security practices, governance requirements and BKMs to comply to Intel security assurance quality.

• Scripting/code writing in System Verilog, Python, C or C++.

Qualifications

What we need to see (Minimum Qualifications):

Possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or similar discipline and 6+ years' experience OR Master's degree in Electrical Engineering, Computer Engineering, or similar discipline and 4+ years' experience OR PhD Degree in Electrical Engineering, Computer Engineering, or similar discipline OR Master's degree in Electrical Engineering, Computer Engineering, or similar discipline and 4+ years' experience OR PhD Degree in Electrical Engineering, Computer Engineering, or similar discipline and 2+ years' experience.

Experience in 2 or more of the following:

• Knowledge of computer architecture: CPU, SOC, chipsets, PCIe based knowledge, platform security, HW security.

• Understanding of security principles, threats and technologies.

• UVM based methodology + verification testbench knowledge.

• Hardware or validation security certification courses.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.