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IBM Process Modeling Research Engineer in ALBANY, New York

Job Description

At IBM Research, we invent things that matter to the world. Today, we are pioneering the most promising and disruptive technologies that will transform industries and society, including the future of AI, Blockchain and Quantum Computing. We are driven to discover. With more than 3,000 researchers in 12 labs located across six continents, IBM Research is one of the world’s largest and most influential corporate research labs.

We are seeking a Process Modeling Research Engineer to join the Advanced Logic & Design Technology Co-Optimization (DTCO) team within IBM Semiconductor Technology Research Organization in Albany, NY. As member of the DTCO Research team, you will be a contributor to state of the art logic technology including technology definition and establishing the value proposition of the technology in terms of power, performance, area, and cost.

You should have one or more of the following skills:

• Experience in Process Integration, semiconductor patterning, and/or semiconductor devices

• Experience in standard cell layout & core design with Industry EDA platform such as Cadence or Synopsys

• Experience in SRAM & SRAM periphery design & optimization

• Experience with parasitic extraction, SPICE & CMOS device architectures

You must be willing to work in any of the following location: Albany, NY

A Masters in Electrical Engineering, Microelectronics, Materials Science or a related area is required. A PhD is preferred.

The World is Our Laboratory: No matter where discovery takes place, IBM researchers push the boundaries of science, technology and business to make the world work better. IBM Research is a global community of forward-thinkers working towards a common goal: progress.

Required Technical and Professional Expertise

  • Masters or PhD in Electrical Engineering, Microelectronics, Materials Science or related area

  • Experience in Process Integration, semiconductor patterning, and/or semiconductor devices

  • Experience in standard cell layout & core design with Industry EDA platform such as Cadence or Synopsys

  • Experience in SRAM & SRAM periphery design & optimization

  • Experience with parasitic extraction, SPICE & CMOS device architectures

Preferred Tech and Prof Experience

  • PhD in Electrical Engineering, Microelectronics, Materials Science or related area

  • Experience with gate-all-around semiconductor technologies

  • Experience optimizing circuit designs for lower power & high performance

  • Demonstrated contributions towards Intellectual Property development

  • Background as a Device, TCAD or Process Integration engineer

EO Statement

IBM is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

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